Field of the Invention
The present invention relates to a semiconductor memory apparatus, and a program method and a program system, and more particularly, to a semiconductor memory apparatus, and a program method and a program system based on writing distribution control of a ReRAM memory.
Discussion of the Related Art
Recently, as devices have rapidly been reduced in size, the number of charges stored in a nonvolatile memory based on the charges, including a flash memory, is limited. Therefore, a resistive random access memory (ReRAM) has been considered as a replacement memory for overcoming this limitation due to reduction in the size of devices. The ReRAM is a nonvolatile memory having a characteristic in which a resistance of a cell is variable by a voltage or a current applied to the cell, and has advantages of having a large margin for sensing data and having a relatively fast speed and low power consumption as compared with other nonvolatile memories. However, since a writing operation in the resistive memory has statistical distribution by a random change like flash memory, voltages switching the resistance are different from each other for each cell, and as a result, when the same writing voltage is applied to all the cells, the writing distribution is increased and thus it is difficult to sense the data.
Studies for controlling the writing distribution in the resistive change memory have been actively conducted.
FIG. 1A is a circuit diagram illustrating a circuit configuration for controlling writing distribution in an existing resistive memory disclosed in Korean Patent Publication No. 10-2010-0013125, and FIG. 1B is a graph illustrating an example of a writing method using the circuit.
Referring to FIGS. 1A and 1B, a read verify circuit is represented by a dotted circle. The read verify circuit compares a voltage (or current) corresponding to a current read from a cell to a reference voltage (or current). As illustrated in FIG. 1B, the cell resistance distribution is controlled by increasing and verifying again a reset voltage applying time. Further, in Korean Patent Publication No. 10-2010-0013125, the circuit is configured to vary the voltage applying time and the voltage magnitude together. However, in the case of Korean Patent Publication No. 10-2010-0013125, when considering the resistance distribution of all the cells, in the case of the worst cell, the number of steps of varying the voltage applying time (or the applying voltage magnitude) may be increased by an allowable maximum number, and therefore, there is a problem in that a writing speed and an unnecessary current consumed in each step are generated.